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KS0724
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
October. 1999. Ver. 0.8
Prepared by:
Jae-Su, Ko
Ko1942@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
KS0724 Specification Revision History Version 0.0 0.1 0.2 0.3 0.4 0.5 Initial version PAD name change (VSS TEST4) Eq2. changed (page 32) Figure 10. Figure 11. Changed Set Static Indicator Register changed (page 46) PAD location added Modify following sections Introduction, Features, Pad Configuration, Pin Description, Power Supply Circuits, Reference Circuit Examples, DC/AC Characteristics, Connection Between KS0724 and LCD Panel Pin name changed at page 8 (FRI FR) Operating VDD is changed Content Date Mar.1999 Mar.1999 Mar.1999 Mar.1999 Apr.1999 Apr.1999
0.6
Apr.1999
0.7 0.8
May.1999 Oct.1999
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................1 FEATURES ..........................................................................................................................................................1 BLOCK DIAGRAM ...............................................................................................................................................3 PAD CONFIGURATION .......................................................................................................................................4 PAD CENTER COORDINATES............................................................................................................................5 PIN DESCRIPTION ..............................................................................................................................................8 POWER SUPPLY..........................................................................................................................................8 LCD DRIVER SUPPLY..................................................................................................................................8 SYSTEM CONTROL .....................................................................................................................................9 MICROPROCESSOR INTERFACE .............................................................................................................11 LCD DRIVER OUTPUTS .............................................................................................................................13 FUNCTIONAL DESCRIPTION............................................................................................................................14 MICROPROCESSOR INTERFACE .............................................................................................................14 DISPLAY DATA RAM (DDRAM) ..................................................................................................................17 LCD DISPLAY CIRCUITS............................................................................................................................20 LCD DRIVER CIRCUIT ...............................................................................................................................22 POWER SUPPLY CIRCUITS ......................................................................................................................23 REFERENCE CIRCUIT EXAMPLES ...........................................................................................................30 RESET CIRCUIT .........................................................................................................................................32 INSTRUCTION DESCRIPTION...........................................................................................................................33 SPECIFICATIONS..............................................................................................................................................48 ABSOLUTE MAXIMUM RATINGS...............................................................................................................48 DC CHARACTERISTICS.............................................................................................................................49 AC CHARACTERISTICS .............................................................................................................................52 REFERENCE APPLICATIONS...........................................................................................................................56 MICROPROCESSOR INTERFACE .............................................................................................................56 CONNECTIONS BETWEEN KS0724 AND LCD PANEL..............................................................................57
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The KS0724 is a single chip driver & controller LSI for graphic dot-matrix liquid crystal display systems. This chip can be connected directly to a microprocessor, accepts serial or 8-bit parallel display data from the microprocessor, stores the display data in an on-chip display data RAM of 65 x 132 bits and generates a liquid crystal display drive signal independent of the microprocessor. It provides a high-flexible display section due to 1to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. It contains 65 common driver circuits and 132 segment driver circuits, so that a single chip can drive a 65 x 132 dot display. And the capacity of the display can be increased through the use of master/slave multi-chip structures. These chip are able to minimize power consumption because it performs display data RAM read / write operation with no external operation clock. In addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high-accuracy voltage regulator circuit, low power consumption voltage divider resistors and OP-Amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems.
FEATURES
Display Driver Output Circuits - - - - 65 common outputs / 132 segment outputs Capacity: 65 x 132 = 8,580 bits RAM bit data "1": a dot of display is illuminated. RAM bit data "0": a dot of display is not illuminated. On-chip Display Data RAM
Applicable Duty Ratios Duty ratio 1/65 1/55 1/49 1/33 Microprocessor Interface - - - High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series Serial interface (only write operation) available Display ON / OFF, set initial display line, set page address, set column address, read status, write / read display data, select segment driver output, reverse display ON / OFF, entire display ON / OFF, select LCD bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for V0 voltage regulation, electronic volume, set static indicator state. H/W and S/W reset available Static drive circuit equipped internally for indicators with 4 flashing modes Applicable LCD bias 1/7 or 1/9 1/6 or 1/8 1/6 or 1/8 1/5 or 1/6 Maximum display area 65 x 132 55 x 132 49 x 132 33 x 132
Various Function Set
- -
1
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Built-in Analog Circuit - - - - - - On-chip oscillator circuit for display clock (external clock can also be used) High performance voltage converter (with booster ratios of x2, x3, x4 and x5, where the step-up reference voltage can be used externally) High accuracy voltage regulator (temperature coefficient: -0.05%/C or external input) Electronic contrast control function (64 steps) Vref = 2.1V 3% (V0 voltage adjustment voltage) High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity)
Operating Voltage Range - - - - - Supply voltage (VDD): 2.4 to 3.6 V LCD driving voltage (VLCD = V0 - VSS): 4.5 to 15.0 V
Low Power Consumption Operating power: 40 typical. (condition: VDD = 3V, x 4 boosting (VCI is VDD), V0 = 11V, internal power supply ON, display OFF and normal mode is selected) Standby power: 10 maximum. (during power save[standby] mode) Wide range of operating temperatures : -40 to 85C
Operating Temperatures
CMOS Process Package Type - Gold bumped chip
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
SEG129 SEG130 SEG131 COM31 COM32 COM63 COMS COMS COM0 SEG0 SEG1 SEG2
:
:
:
:
VDD V0 V1 V2 V3 V4 VSS
33 COMMON DRIVER CIRCUITS
132 SEGMENT DRIVER CIRCUITS
33 COMMON DRIVER CIRCUITS
DISPLAY DATA CONTROL CIRCUIT V/F CIRCUIT PAGE I/O ADDRESS BUFFER CIRCUIT V/R CIRCUIT
COMMON OUTPUT CONTROLLER CIRCUIT
HPMB
V0 VR INTRS REF VEXT
DISPLAY DATA RAM 65 X 132 = 8,580 Bits
LINE ADDRESS CIRCUIT
DISPLAY TIMING GENERATOR CIRCUIT
COLUMN ADDRESS CIRCUIT
MS CL M FRS FR DISP DUTY0 DUTY1
VOUT C1C1+ C2C2+ C3+ C4+ VCI OSCILLATOR CLS
V/C CIRCUIT
STATUS REGISTER BUS HOLDER
INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
TEST1 TEST2 TEST3 TEST4 DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) C68 RESETB PS RW_WRB E_RD RS CS2 CS1B
Figure 1. Block Diagram
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
PAD CONFIGURATION
285 138
- - - - - - - - - -
Y (TOP VIEW)
- - - -
- - - -
286
137
KS0724
(0,0)
X
313
- - - - - - - - - -
1 109
110
Figure 2. KS0724 Chip Configuration Table 1. KS0724 Pad Dimensions Item Chip size Pad No. 1 to 109 110 to 137, 140 to 283 287 to 313 137 to 139, 284 to 286 1 to 109 110 to 136 Bumped pad size 140 to 283 287 to 313 138,139,284,285 137, 286 Bumped pad height COG Align Key Coordinate
30m 30m 30m 30m 30m 30m 30m 30m 30m
Size X 9680 70 60 80 50 122 40 122 60 122 14 (Typ.) ILB Align Key Coordinate
42m 108m
Y 2030
Unit
Pad pitch
100 40 122 40 122 60 m
All pad
108m
42m
(-4170, +427) 60m
(+4170, +427)
42m
42m
(-4040, -529)
30m
(+4040, -544)
108m
108m
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates [Unit: m] Pad No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad name
FRS FR TEST1 TEST2 TEST3 M CL DISP VSS VSS CS1B CS2 VDD RESETB RS VSS RW_WRB E_RDB VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD DUTY0 DUTY1 VSS VDD VDD VDD VDD VDD VCI VCI VCI VSS VSS VSS VSS VSS VOUT VOUT VOUT VOUT C4+
X
-3780 -3710 -3640 -3570 -3500 -3430 -3360 -3290 -3220 -3150 -3080 -3010 -2940 -2870 -2800 -2730 -2660 -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1820 -1750 -1680 -1610 -1540 -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350
Y
-879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879
Pad No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad name
C4+ C4+ C4+ C3+ C3+ C3+ C3+ C1C1C1C1C1+ C1+ C1+ C1+ C2+ C2+ C2+ C2+ C2C2C2C2VDD VEXT VEXT REF VSS V1 V1 V1 V2 V2 V2 V3 V3 V3 V4 V4 V4 V0 V0 V0 VR VR VR VSS VSS VDD MS
X
-280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 2030 2100 2170 2240 2310 2380 2450 2520 2590 2660 2730 2800 2870 2940 3010 3080 3150
Y
-879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879 -879
Pad No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad name
CLS VSS C68 PS VDD HPMB VSS INTRS VDD COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 DUMMY1 DUMMY2 DUMMY3 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 SEG3 SEG4
X
3220 3290 3360 3430 3500 3570 3640 3710 3780 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4693 4470 4390 4310 4250 4190 4130 4070 4010 3930 3870 3810 3750 3690
Y
-879 -879 -879 -879 -879 -879 -879 -879 -879 -780 -720 -660 -600 -540 -480 -420 -360 -300 -240 -180 -120 -60 0 60 120 180 240 300 360 420 480 540 600 660 720 780 860 868 868 868 868 868 868 868 868 868 868 868 868 868
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Table 2. Pad Center Coordinates (Continued) [Unit: m] Pad No.
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad name
SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54
X
3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690
Y
868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868
Pad No.
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad name
SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104
X
630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310
Y
868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868
Pad No.
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad name
SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM32 COM33 COM34 COM35 COM36 COM37 DUMMY4 DUMMY5 DUMMY6 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51
X
-2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -4010 -4070 -4130 -4190 -4250 -4310 -4390 -4470 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693
Y
868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 868 860 780 720 660 600 540 480 420 360 300 240 180 120 60 0
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued) [Unit: m] Pad No.
301 302 303 304 305 306 307 308 309 310 311 312 313
Pad name
COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
X
-4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693 -4693
Y
-60 -120 -180 -240 -300 -360 -420 -480 -540 -600 -660 -720 -780
Pad No.
Pad name
X
Y
Pad No.
Pad name
X
Y
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pins Description Name VDD VSS I/O Supply Supply Power supply Ground LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias V1 V2 V3 V4 1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 Description
V0 V1 V2 V3 V4
I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pins Description Name C1C1+ C2C2+ C3+ C4+ VOUT VR VCI I/O O O O O O O I/O I I Description Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Capacitor 4 positive connection pin for voltage converter Voltage converter input / output pin Connect this pin to VSS through capacitor. V0 voltage adjustment pin It is valid only when internal voltage regulator resistors are not used (INTRS = "L"). This is the reference voltage for the voltage converter circuit for the LCD drive. Whether internal voltage converter use or not use, this pin should be fixed. The voltage should have the following range: 2.4V VCI 3.6V This is the externally input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used (REF = "L"). When using internal VREF, this pin is Open Select the external VREF voltage via VEXT pin - REF = "L": using the external VREF - REF = "H": using the internal VREF
VEXT
I
REF
I
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL
Table 5. System Control Pins Description Name I/O Description Master / slave mode select input Master makes some signals for display, and slave gets them. This is for display synchronization. - MS = "H": master mode - MS = "L": slave mode The following table depends on the MS status. MS I MS CLS H L OSC circuit Enabled Disabled Disabled Power supply circuit Enabled Enabled Disabled CL Output Input Input M Output Output Input FR Output Output Output DISP Output Output Input
H L
CLS
I
Built-in oscillator circuit enable / disable select pin - CLS = "H": enable - CLS = "L": disable (external display clock input to CL pin) Display clock input / output pin When the KS0724 is used in master/slave mode (multi-chip), the CL pins must be connected each other. LCD AC Signal input / output pin When the KS0724 is used in master/slave mode (multi-chip), the M pins must be connected each other. - MS = "H": output - MS = "L": input Static driver segment output pin This pin is used together with the FR pin. Static driver common output pin This pin is used together with the FRS pin. LCD display blanking control input / output When KS0724 is used in master / slave mode (multi-chip), the DISP pins must be connected each other. - MS = "H": output - MS = "L": input Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level and is valid only in master operation. - INTRS = "H": use the internal resistors - INTRS = "L": use the external resistors V0 voltage is controlled by VR pin and external resistive divider.
CL
I/O
M
I/O
FRS FR
O O
DISP
I/O
INTRS
I
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Table 5. System Control Pins Description (Continued) Name I/O Description The LCD driver duty ratio depends on the following table. DUTY1 DUTY0 DUTY1 L I L H H DUTY0 L H L H Duty ratio 1/33 1/49 1/55 1/65
HPMB
I
Power control pin of the power supply circuits for LCD driver - HPMB = "H": normal mode - HPMB = "L": high power mode This pin is valid only in master operation.
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pins Description Name RESETB I/O I Description Reset input pin When RESETB is "L", initialization is executed. Parallel / Serial data input select input PS H L Interface mode Parallel Serial Chip select CS1B, CS2 CS1B, CS2 Data / instruction RS RS Data DB0 to DB7 SID (DB7) Read / Write E_RDB RW_WRB Write only Serial clock SCLK (DB6)
PS
I
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RDB and RW_WRB must be fixed to either "H" or "L". C68 CS1B CS2 RS I Microprocessor Interface Select input pin in parallel mode - C68 = "H": 6800-series MPU interface - C68 = "L": 8080-series MPU interface Chip select input pins Data / instruction I/O is enabled only when CS1B is "L" and CS2 is "H". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data - RS = "L": DB0 to DB7 are control data Read / Write execution control pin C68 H RW_WRB I L 8080-series /WRB MPU Type 6800-series RW_WRB RW Description Read / Write control input pin - RW = "H": read - RW = "L": write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WRB signal.
I
I
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Table 6. Microprocessor Interface Pins Description (Continued) Name I/O Read / Write execution control pin C68 MPU Type E_RDB Description Read / Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RDB is "L", DB0 to DB7 are in an output status. Description
E_RDB
I
H
6800-series
E
L
8080-series
/RDB
DB0 to DB7 TEST1 to TEST3
I/O
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance. These are pins for IC chip testing. They are set to Open.
I/O
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 7. LCD Driver Output Pins Description Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG131 H O H L L Power save mode M H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM63 H O H L L Power save mode M H L H L Common driver output voltage VSS V0 V1 V4 VSS
COMS
O
Common output for the icons The output signals of two pins are same. When not used, these pins should be left Open. In multi-chip (master / slave) mode, all COMS pin on both master and slave units are the same signal.
NOTE: DUMMY - These pins should be opened (floated).
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There are CS1B and CS2 pins for chip selection. The KS0724 can interface with an MPU only when CS1B is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface KS0724 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode PS H L Type Parallel Serial CS1B CS1B CS1B CS2 CS2 CS2 C68 H L *x Interface mode 6800-series MPU mode 8080-series MPU mode Serial-mode
*x: Don't care
Parallel interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in Table 10. Table 9. Microprocessor Selection for Parallel Interface C68 H L CS1B CS1B CS1B CS2 CS2 CS2 RS RS RS E_RDB E /RDB RW_WRB RW /WRB DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series
Table 10. Parallel Data Transfer Common RS H H L L 6800-series E_RDB (E) H H H H RW_WRB (RW) H L H L 8080-series E_RDB (/RDB) L H L H RW_WRB (/WRB) H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction)
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS = "L") When the KS0724 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing Busy Flag The Busy Flag indicates whether the KS0724 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance. Data Transfer The KS0724 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
MPU signals
RS
/WRB
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WRB N D(N) D(N+1) D(N+2) D(N+3)
BUS HOLDER
COLUMN ADDRESS
N
N+1
N+2
N+3
Figure 4. Write Timing
MPU signals
RS /WRB /RDB DB0 to DB7 N Dummy D(N) D(N+1)
Internal signals
/WRB /RDB BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3
Figure 5. Read Timing
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker.
DB0 DB1 DB2 DB3 DB4
0 1 0 1 0
0 0 1 0 0
1 0 1 1 0
------
0 1 0 0 1
COM0 COM1 COM2 COM3 COM4 LCD Display
------
Display Data RAM
Figure 6. RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a Page Address to DISPLAY-DATA-RAM shown in figure 8. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0 are "L") is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the 132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access Line Address of icons.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Column Address Circuit Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is independent of page address register. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to the following figure 7. SEG output Column address [Y7:Y0] Display data LCD panel display (ADC = 0) SEG 0 00H 1 SEG 1 01H 0 SEG 2 02H 1 SEG 3 03H 0 ... ... ... ... ... ... SEG 128 80H 1 SEG 129 81H 1 SEG 130 82H 0 SEG 131 83H 0
LCD panel display ( ADC = 1 )
... ...
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Page Address
DB3 DB2 DB1 DB0
Data
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 00 01 02 03 04 05 83 82 81 80 7F 7E SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
0
0
0
0
Page0
1/49 Duty
0
0
0
1
Page1
0
0
1
0
Page2
0
0
1
1
Page3
Start
0
1
0
0
Page4
0
1
0
1
Page5
0
1
1
0
Page6
1
0
Column Address
0
0
Page8
ADC=0 ADC=1
-------------
7E 7F 80 81 82 83 05 04 03 02 01 00 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
LCD Output
When the initial display line address is 1C[HEX]
Figure 8. Display Data RAM Map
1/33 Duty
0
1
1
1
Page7
1/55 Duty
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
LCD DISPLAY CIRCUITS
Oscillator This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. The oscillator circuit is only enabled when MS = "H" and CLS = "H". When on-chip oscillator is not used, CLS pin must be "L" condition. In this time, external clock must be input from CL pin Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL generated by oscillation clock, generates a clock to the line counter and a latch signal to the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the display data latch circuit in synchronization with the display clock. The display data which is read to the LCD driver is completely independent of the access to the display data RAM from the microprocessor. The LCD AC signal, M is generated from the display clock. 2-frame AC driver waveforms with internal timing signal are shown in figure 9. In a multiple chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11 shows the M, SYNC, CL, and DISP status. Table 11. Master and Slave Timing Signal Status Operation mode Master Slave Oscillator ON (internal clock used) OFF(external clock used) M Output Output Input CL Output Input Input DISP Output Output Input
64
65
1
2
3
4
5
6
7
8
9
10
11
12
58
59
60
61
62
63
64
65
1
2
3
4
5
6
CL FR
COM0
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM1
SEGn
Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/65)
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL select Instruction specifies the scanning direction of the common output pins. Table 12. The Relationship between Duty Ratio and Common Output Common output pins Duty SHL 0 1 0 1 COM COM [0:15] [16:23] COM[0:15] COM[31:16] COM[0:23] COM[47:24] COM[0:26] COM[53:27] COM [24:26] COM [27:36] *NC *NC *NC *NC *NC *NC COM[0:63] COM[63:0] COM [37:39] COM COMS [48:63] COM[16:31] COMS COM[15:0] COM[24:47] COMS COM[23:0] COM[27:53] COMS COM[26:0] COMS *NC: No Connection COM [40:47]
1/33 1/49 1/55 1/65
0 1
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
LCD DRIVER CIRCUIT
This driver circuit is configured by 66-channel (including 2 COMS channels) common driver and 132-channel segment driver. This LCD panel driver voltage depends on the combination of display data and FR signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD
FR
VSS V0 V1 V2
COM0
V3 V4 VSS V0 V1 V2
COM1
V3 V4 VSS V0 V1 V2
COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4
COM2
V3 V4 VSS V0 V1 V2
SEG0
V3 V4 VSS V0 V1 V2
SEG1
V3 V4 VSS V0 V1 V2
SEG2
V3 V4 VSS
Figure 10. Segment and Common Timing
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 13 shows the referenced combinations in using Power Supply circuits. Table 13. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4
Open
Open
Open
011
OFF
ON
ON
External input
Open
Open
001 000
OFF OFF
OFF OFF
ON OFF
Open Open
External input External input
Open External input
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Voltage Converter Circuits These circuits boost up the electric potential between VCI and VSS to 2, 3, 4 or 5 times toward positive side and boosted voltage is outputted from VOUT pin. [C1 = 1.0 to 4.7 F]
VDD VCI VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VCI VSS
VDD VCI VCI
+ C1
VSS VOUT C4+ C3+ C1-
C1 +
VOUT= 3 x VCI
+
C1 + + C1
C1
VOUT= 2 x VCI
C1+ C2+ C2-
VCI VSS
Figure 11. Two Times Boosting Circuit
Figure 12. Three Times Boosting Circuit
VDD VCI VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2+ C1 C1 + + C1 + C1 VOUT= 4 x VCI
VDD VCI VCI VSS VOUT C4+ C3+ C1C1+ VCI VSS C2+ C2+ + C1 C1 C1 + VOUT= 5 x VCI
+ C1 + C1 VCI VSS
Figure 13. Four Times Boosting Circuit
Figure 14. Five Times Boosting Circuit
* The VCI voltage range must be set so that the VOUT voltage does not exceed the absolute maximum rated value
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 15, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25C is shown in table 14-1. Rb V0 = ( 1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - ) VEV = ( 1 - ) x VREF [V] ------ (Eq. 2) 162 Table 14-1. VREF Voltage at Ta = 25 C REF H L Temp. coefficient -0.05% / C External input VREF [V] 2.1 VEXT
Table 14-2. Electronic Contrast Control Register (64 Steps) SV5 0 0 : : 1 : : 1 1 SV4 0 0 : : 0 : : 1 1 SV3 0 0 : : 0 : : 1 1 SV2 0 0 : : 0 : : 1 1 SV1 0 0 : : 0 : : 1 1 SV0 0 1 : : 0 : : 0 1 Reference voltage parameter () 0 1 : : 32 (default) : : 62 63 Maximum High : : : : : : : : : : V0 Minimum Contrast Low
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
VOUT
+ VEV Rb VR V0
Ra VSS
GND
Figure 15. Internal Voltage Regulator Circuit
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
In Case of Using Internal Resistors, Ra and Rb. (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15. Internal Rb / Ra Ratio depending on 3-bit Data ( R2 R1 R0 ) 3-bit data settings (R2 R1 R0) 000 1+(Rb / Ra) 3.0 001 3.5 010 4.0 011 4.5 100 5.0 101 5.5 110 6.0 111 6.4
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C.
16.00 14.00 12.00 10.00 V0 8.00 [V] 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 Electronic volume level
Figure 16. Electronic Volume Level
(1 (1 (1 (1 (0 (0 (0 (0
1 1 0 0 1 1 0 0
1) 0) 1) 0) 1) 0) 1) 0)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
In Case of Using External Resistors, Ra and Rb. (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 10 = ( 1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 2 (63 - 32) VEV = ( 1 - ) x 2.1 1.698 [V] ------ (Eq. 4) 162 From requirement 3. 10 = 1 [uA] ------ (Eq. 5) Ra + Rb
From equations Eq. 3, 4 and 5 Ra 1.69 [M] Rb 8.31 [M] The following table shows the range of V0 depending on the above requirements. Table 16. V0 Depending on Electronic Volume Level Electronic volume level 0 V0 7.57 ....... ....... 32 10.00 ....... ....... 63 12.43
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are converted by the Voltage Follower for increasing drive capability. The following table shows the relationship between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 Level and Duty Ratio Duty ratio 1/33 1/49 1/55 1/65 DUTY1 L L H H DUTY0 L H L H LCD bias 1/5 1/6 1/6 1/8 1/6 1/8 1/7 1/9 V1 (4/5) x V0 (5/6) x V0 (5/6) x V0 (7/8) x V0 (5/6) x V0 (7/8) x V0 (6/7) x V0 (8/9) x V0 V2 (3/5) x V0 (4/6) x V0 (4/6) x V0 (6/8) x V0 (4/6) x V0 (6/8) x V0 (5/7) x V0 (7/9) x V0 V3 (2/5) x V0 (2/6) x V0 (2/6) x V0 (2/8) x V0 (2/6) x V0 (2/8) x V0 (2/7) x V0 (2/9) x V0 V4 (1/5) x V0 (1/6) x V0 (1/6) x V0 (1/8) x V0 (1/6) x V0 (1/8) x V0 (1/7) x V0 (1/9) x V0
High Power Mode The power supply circuit equipped in the KS0724 for LCD drive has very low power consumption (in normal mode: HPMB = "H"). If use for LCD panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPMB pin to "L" (high power mode) can improve the quality of the display. Moreover, if the quality of display is inadequate even after High Power mode has been set, then it is necessary to add a liquid crystal drive power supply externally (Vout or V0 or V1 / V2 / V3 / V4).
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
REFERENCE CIRCUIT EXAMPLES
When using internal regulator resistors VDD MS INTRS VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VR + + + + + V0 V1 V2 V3 V4
When not using internal regulator resistors VDD MS INTRS VCI VSS VOUT C4+ C3+ C1C1+ C2+ C2VR V0 V1 V2 V3 V4 VSS
C1 C1 C1 C1 C2 C2 C2 C2 C2 VSS -
C1 C1 C1 C1 Ra C2 C2 C2 C2 C2 VSS + + + + + Rb
Figure 17. When Using all Internal LCD Power Circuits (VCI = VDD, 4-time V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors VDD MS INTRS VCI VOUT C4+ C3+ C1C1+ C2+ C2VR C2 C2 C2 C2 C2 VSS + + + + + V0 V1 V2 V3 V4
When not using internal regulator resistors VDD MS INTRS VCI VOUT C4+ C3+ C1C1+ C2+ C2VSS
External Power Supply
External Power Supply
Ra C2 C2 C2 C2 C2 VSS VR + Rb V0 + V1 + V2 + V3 + V4
Figure 18. When Using some Internal LCD Power Circuits (VCI = VDD, V/C: OFF, V/R: ON, V/F: ON)
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
VDD MS INTRS VCI VOUT C4+ C3+ C1C1+ C2+ C2VR C2 C2 C2 C2 C2 VSS + + + + + V0 V1 V2 V3 V4
External Power Supply
Figure 19. When Using some Internal LCD Power Circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: ON)
VDD MS INTRS VCI VOUT C4+ C3+ C1C1+ C2+ C2VR External Power Supply VSS V0 V1 V2 V3 V4
Value of external Capacitance Item C1 C2 Value 1.0 to 4.7 0.47 to 1.0 Unit F
Figure 20. When Not Using any Internal LCD Power Supply Circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: OFF) * C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
RESET CIRCUIT
Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/8 (1/49 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, following procedure is occurred. Read-modify-write: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release While RESETB is "L" or Reset instruction is executed, no instruction except read status could be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 18. Instruction Table x: Don't care Instruction
Display ON / OFF Initial display line Set page address Set column address MSB Set column address LSB Read status Write display data RS 0 0 0 0 0 0 1 RW 0 0 0 0 0 1 0 DB7 1 0 1 0 0 BUSY DB6 0 1 0 0 0 ADC DB5 1 ST5 1 0 0 ON/OFF DB4 0 ST4 1 1 0 RESETB DB3 1 ST3 P3 Y7 Y3 0 DB2 1 ST2 P2 Y6 Y2 0 DB1 1 ST1 P1 Y5 Y1 0 DB0 DON ST0 P0 Y4 Y0 0
Description
Turn on/off LCD panel When DON = 0: display OFF When DON = 1: display ON Specify DDRAM line for COM0 Set page address Set column address MSB Set column address LSB Read the internal status Write data into DDRAM
Write data
Read display data
1
1
Read data
Read data from DDRAM Select SEG output direction When ADC = 0: normal direction (SEG0SEG131) When ADC = 1: reverse direction (SEG131SEG0) Select normal / reverse display When REV = 0: normal display When REV = 1: reverse display Select normal/entire display ON When EON = 0: normal display. When EON = 1: entire display ON Select LCD bias Set modify-read mode release modify-read mode Initialize the internal functions Select COM output direction When SHL = 0: normal direction (COM0COM63) When SHL = 1: reverse direction (COM63COM0) Control power circuit operation Select internal resistance ratio of the regulator resistor Set reference voltage mode Set reference voltage register Set static indicator mode Set static indicator register Compound Instruction of display OFF and entire display ON
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF LCD bias select Set modify-read Reset modify-read Reset
0 0 0 0 0
0 0 0 0 0
1 1 1 1 1
0 0 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 1 0
1 0 0 1 0
0 1 0 1 1
EON BIAS 0 0 0
SHL select
0
0
1
1
0
0
SHL
x
x
x
Power control Regulator resistor select Set reference voltage mode Set reference voltage register Set static indicator mode Set static indicator register Power save
0 0 0 0 0 0 -
0 0 0 0 0 0 -
0 0 1 x 1 x -
0 0 0 x 0 x -
1 1 0 SV5 1 x -
0 0 0 SV4 0 x -
1 0 0 SV3 1 x -
VC R2 0 SV2 1 x -
VR R1 0 SV1 0 S1 -
VF R0 1 SV0 SM S0 -
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Table 18. Instruction Table (Continued) x: Don't care Instruction
NOP Test Instruction_1 Test Instruction_2 RS 0 0 0 RW 0 0 0 DB7 1 1 1 DB6 1 1 0 DB5 1 1 0 DB4 0 1 1 DB3 0 x x DB2 0 x x DB1 1 x x DB0 1 x x
Description
Non-Operation command Don't use this instruction Don't use this instruction
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Display ON / OFF Turns the Display ON or OFF RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
0 0 DON = 1: display ON DON = 0: display OFF Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS 0 ST5 0 0 : 1 1 Set Page Address Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. RS 0 P3 0 0 : 0 1 RW 0 DB7 1 P2 0 0 : 1 0 DB6 0 DB5 1 P1 0 0 : 1 0 DB4 1 DB3 P3 P0 0 1 : 1 0 DB2 P2 DB1 P1 Page 0 1 : 7 8 DB0 P0 RW 0 ST4 0 0 : 1 1 DB7 0 ST3 0 0 : 1 1 DB6 1 ST2 0 0 : 1 1 DB5 ST5 ST1 0 0 : 1 1 DB4 ST4 ST0 0 1 : 0 1 DB3 ST3 DB2 ST2 DB1 ST1 DB0 ST0
Line address 0 1 : 62 63
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Set Column Address Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS RW DB7 0 0 0
DB6 0
DB5 0
DB4 1
DB3 Y7
DB2 Y6
DB1 Y5
DB0 Y4
Set Column Address LSB RS RW DB7 0 Y7 0 0 : 1 1 Read Status 0 Y6 0 0 : 0 0 0 Y5 0 0 : 0 0
DB6 0 Y4 0 0 : 0 0
DB5 0 Y3 0 0 : 0 0
DB4 0 Y2 0 0 : 0 0
DB3 Y3 Y1 0 0 : 1 1
DB2 Y2 Y0 0 1 : 0 1
DB1 Y1
DB0 Y0
Column address 0 1 : 130 131
Indicates the internal status of the KS0724 RS 0 RW 1 DB7 BUSY DB6 ADC DB5 ON / OFF DB4 RESETB DB3 0 DB2 0 DB1 0 DB0 0
Flag BUSY
Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. Indicates the relationship between RAM column address and segment driver 0: reverse direction (SEG131 SEG0), 1: normal direction (SEG0 SEG131) Indicates display ON / OFF status 0: display ON, 1: display OFF Indicates the initialization is in progress by RESETB signal 0: chip is active, 1: chip is being reset
ADC ON / OFF RESETB
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Write Display Data 8-bit data of display data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write data
Set Page Address Set Column Address Data Write Column = Column + 1 YES
Set Page Address Set Column Address Dummy Data Read Column = Column + 1 Data Read Column = Column + 1 YES
Data Write Continue ? NO Optional Status
Data Read Continue ? NO Optional Status
Figure 21. Sequence for Writing Display Data Data Read Display Data
Figure 22. Sequence for Reading Display Data
8-bit data from display data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read data
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
ADC Select (Segment Driver Direction Select) Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
0 0 1 0 1 ADC = 0: normal direction (SEG0 SEG131) ADC = 1: reverse direction (SEG131 SEG0) Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 REV 0 (normal) 1 (reverse) Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
RAM bit data = "1" LCD pixel is illuminated LCD pixel is not illuminated
RAM bit data = "0" LCD pixel is not illuminated LCD pixel is illuminated
0 0 1 EON = 0: normal display EON = 1: entire display ON Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 LCD bias Bias = 0 1/6 1/8 1/8 1/9 Bias = 1 1/5 1/6 1/6 1/7 DB2 0 DB1 1 DB0 Bias
Duty ratio 1/33 1/49 1/55 1/65
DUTY1 0 0 1 1
DUTY0 0 1 0 1
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS 0 Reset Modify-Read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify-read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Set Page Address Set Column Address (N) Set Modify-Read Dummy Read Data Read Data Process Data Write NO
Change Complete ? YES Reset Modify-Read Return Column Address (N)
Figure 23. Sequence for Cursor Display
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
SHL Select (Common Output Mode Select) COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x x: Don't care
SHL = 0: normal direction (COM0 COM63) SHL = 1: reverse direction (COM63 COM0) Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
VC 0 1
VR
VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON
0 1 0 1
Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Regulator Resistor Select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS 0 R2 0 0 0 0 1 1 1 1 RW 0 R1 0 0 1 1 0 0 1 1 DB7 0 R0 0 1 0 1 0 1 0 1 DB6 0 DB5 1 DB4 0 DB3 0 (1 + Rb / Ra) ratio 3.0 3.5 4.0 4.5 5.0 (default) 5.5 6.0 6.4 DB2 R2 DB1 R1 DB0 R0
Reference Voltage Select Consists of 2-byte instruction. The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The 1st Instruction: Set Reference Voltage Select Mode RS RW DB7 DB6 DB5 DB4 0 0 1 0 0 0
DB3 0
DB2 0
DB1 0
DB0 1
The 2nd Instruction: Set Reference Voltage Register RS RW DB7 DB6 DB5 0 0 x x SV5
DB4 SV4
DB3 SV3
DB2 SV2
DB1 SV1
DB0 SV0
SV5 0 0 : : 1 : : 1 1
SV4 0 0 : : 0 : : 1 1
SV3 0 0 : : 0 : : 1 1
SV2 0 0 : : 0 : : 1 1
SV1 0 0 : : 0 : : 1 1
SV0 0 1 : : 0 : : 0 1
Reference voltage parameter () 0 1 : : 32 (default) : : 62 63
V0 Minimum : : : : : Maximum
Contrast Low : : : : : High
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Setting Reference V oltage Start 1 Instruction for Mode Setting 2
nd st
Instruction for Register Setting
Setting Reference V oltage E n d
Figure 24. Sequence for Setting the Reference Voltage Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator register) to be valid. The first byte sets the Static Indicator ON / OFF. When it is ON, the second byte updates the contents of Static Indicator register without issuing any other instruction and this Static Indicator state is released after setting the data of indicator register. The 1st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 0 0 1 SM = 0: static indicator OFF SM = 1: static indicator ON 0 1 0
DB3 1
DB2 1
DB1 0
DB0 SM
The 2nd Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 0 S1 0 0 1 1 NOP Non Operation Instruction RS 0 RW 0 DB7 1 DB6 1 DB5 1 0 x S0 0 1 0 1 x x
DB4 x
DB3 x
DB2 x
DB1 S1
DB0 S0
Status of static indicator output OFF ON (about 1 second blinking) ON (about 0.5 second blinking) ON (always ON)
DB4 0
DB3 0
DB2 0
DB1 1
DB0 1
Test Instruction (Test Instruction_1 & Test Instruction_2) These are the instruction for IC chip testing. Please do not use it. If the Test Instruction is used by accident, it can be cleared by applying "0" signal to the RESETB input pin or the reset instruction. RS 0 0 RW 0 0 DB7 1 1 DB6 1 0 DB5 1 0 DB4 1 1 DB3 x x DB2 x x DB1 x x DB0 x x
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Power Save (Compound Instruction) If the entire display ON / OFF instruction is issued during the display OFF state, KS0724 enters the Power Save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, Power Save is entered to one mode of sleep and standby mode. When Static Indicator mode is ON, standby mode is issued. When OFF, sleep mode is issued. Power Save mode is released by the entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction) [Display OFF] [Entire Display ON]
Sleep Mode [Oscillator Circuit: OFF] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <2uA]
Standby Mode [Oscillator Circuit: ON] [LCD Power Supply Circuit: OFF] [All COM / SEG Outputs: VSS] [Consumption Current: <10uA]
Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] 2 Bytes Command
Power Save OFF [Entire Display OFF]
Release Sleep Mode
Release Standby Mode
Figure 25. Power Save (Compound Instruction) - Sleep Mode This stops all operations in the LCD display system, and as long as there are no access from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: a. The oscillator circuit and the LCD power supply circuit are halted. b. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level. - Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. b. The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs a VSS level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Referential Instruction Setup Flow (1)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H "
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User L C D P ower Setup by Internal Instructions [Voltage Converter ON] Waiting for 1ms User L C D P ower Setup by Internal Instructions [Voltage Regulator ON] Waiting for 1ms User L C D P ower Setup by Internal Instructions [Voltage Follower ON]
User L C D P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister Set]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 26. Initializing with the Built-in Power Supply Circuits
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (2)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = "L"
Waiting for Stabilizing the Power
RESETB Pin = "H"
Set Power Save
User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select]
User LCD Power Setup by Internal Instructions [Regulator Resistor Select] [Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 27. Initializing without the Built-in Power Supply Circuits
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Referential Instruction Setup Flow (3)
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display ON / OFF by Instruction [Display ON / OFF]
Turn Display ON / OFF by Instruction [Display ON / OFF]
End of Data Display
Figure 28. Data Displaying
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (4)
Optional Status
Turn Display ON /OFF by Instruction [Display OFF]
User LCD Power Setup by Internal Instructions [Voltage Regulator OFF] Waiting for 50ms User LCD Power Setup by Internal Instructions [Voltage Follower OFF] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Converter OFF] Waiting for 1ms Power OFF (VDD-VSS)
Figure 29. Power OFF
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings Parameter Supply voltage range Input voltage range Operating temperature range Storage temperature range
NOTES: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages V0 V1 V2 V3 V4 VSS must always be satisfied.(VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Symbol VDD VLCD VIN TOPR TSTR
Rating - 0.3 to +7.0 - 0.3 to +17.0 - 0.3 to VDD + 0.3 - 40 to +85 - 55 to +125
Unit V V V C C
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
DC CHARACTERISTICS
Table 20. DC Characteristics (VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85C) Item Operating voltage (1) Operating voltage (2) High Input voltage Low Output voltage High Low VIL VOH VOL IIL IOZ RON fOSC fCL IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C Duty ratio = 1/65 x2 Voltage converter input voltage VCI x3 x4 x5 Voltage converter output voltage Voltage regulator operating voltage Voltage follower operating voltage Reference voltage VOUT x2 / x3 / x4 / x5 voltage conversion (no-load ) VSS 0.8VDD VSS - 1.0 - 3.0 32.7 4.09 2.4 2.4 2.4 2.4 95 2.0 43.6 5.45 99 0.2VDD VDD V 0.2VDD + 1.0 + 3.0 3.0 54.5 6.81 3.6 3.6 V 3.6 3.2 % VOUT VCI A A k kHz *5 *6 SEGn COMn *7 CL *8 *4 Symbol VDD V0 VIH Condition Min. 2.4 4.5 0.8VDD Typ. Max. 3.6 15.0 VDD V *3 Unit V V Pin used VDD *1 V0 *2
Input leakage current Output leakage current LCD driver ON resistance Oscillator frequency Internal External
VOUT V0 VREF Ta = 25C - 0.05%/C
6.0 4.5 2.04
2.1
16.0 15.0 2.16
V V V
VOUT V0 *9 *10
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Dynamic Current Consumption (1) when the Built-in Power Circuit is OFF (At Operate Mode) (Ta = 25C) Item Dynamic current consumption (1) Symbol IDD1 Condition VDD = 3.0V V0 - VSS = 11.0V 1/65 duty ratio Display pattern OFF Min. Typ. Max. Unit Pin used
-
15
23
*11
Dynamic Current Consumption (2) when the Built-in Power Circuit is ON (At Operate Mode) (Ta = 25C) Item Symbol Condition VDD = 3.0V, (VCI = VDD, 4 times boosting) V0 - VSS = 11.0V, 1/65 duty ratio, Display pattern OFF, Normal power mode IDD2 VDD = 3.0V, (VCI = VDD, 4 times boosting) V0 - VSS = 11.0V, 1/65 duty ratio, Display pattern checker, Normal power mode Min. Typ. Max. Unit Pin used
-
40
60
*12
Dynamic current consumption (2)
-
150
200
*12
Current Consumption during Power Save Mode (Ta = 25C) Item Sleep mode current Standby mode current Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. 2.0 10.0 Unit A A Pin used
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 21. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio Item On-chip oscillator circuit is used 1/65 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/55 On-chip oscillator circuit is not used On-chip oscillator circuit is used 1/49 On-chip oscillator circuit is not used On-chip oscillator circuit is used On-chip oscillator circuit is not used fCL fOSC
fFR fOSC 2 x 8 x 65 fOSC

8 External input (fCL) fOSC
2 x 65 fOSC
9 External input (fCL) fOSC
2 x 9 x 55 fOSC
2 x 55 fOSC
10 External input (fCL) fOSC
2 x 10 x 49 fOSC
2 x 49 fOSC
1/33
15 External input (fCL)
2 x 15 x 33 fOSC
2 x 33 (fOSC: oscillation frequency, fCL: display clock frequency, fFR: LCD AC signal frequency)
[* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RDB, RW_WRB, RESETB, MS, C68, PS, INTRS, HPMB, CLS, CL, M, FR, DISP pins. *4. DB0 to DB7, M, FR, DISP, CL pins. *5. CS1B, CS2, RS, DB[7:0], E_RDB, RW_WRB, RESETB, MS, C68, PS, INTRS, HPMB, CLS, CL, M, FR, DISP pins. *6. Applies when the DB[7:0], M, FR, DISP, and CL pins are in high impedance. *7. Resistance value when 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON= V / 0.1 [k] (V: voltage change when 0.1[mA] is applied in the ON status.) *8. See table 21 for the relationship between oscillation frequency and frame frequency. *9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range *10. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS tAS80 CS1B (CS2=1) tPW80(R), RDB, WRB 0.9VDD 0.1VDD tDS80 DB0 to DB7 (Write) tACC80 DB0 to DB7 (Read) tOD80 tDH80 tPW80(W) tAH80
tCY80
Figure 30. Read / Write Characteristics (8080-series MPU)
Item Address setup time Address hold time System cycle time Pulse width (WRB) Pulse width (RDB) Data setup time Data hold time Read access time Output disable time
Signal RS RS RW_WRB E_RDB DB7 to DB0
Symbol tAS80 tAH80 tCY80 tPW80(W) tPW80(R) tDS80 tDH80 tACC80 tOD80
Min. 0 0 300 60 60 40 15 10
(VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Max. Unit Remark 140 100 ns ns ns ns ns ns CL = 100 pF
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Read / Write Characteristics (6800-series Microprocessor)
RS tAS68 CS1B (CS2=1) tPW68(R), tPW68(W) E 0.1VDD 0.9VDD tDS68 DB0 to DB7 (Write) tACC68 DB0 to DB7 (Read) tOD68 tDH68 tAH68
tCY68
Figure 31. Read / Write Characteristics (6800-series Microprocessor)
Item Address setup time Address hold time System cycle time Data setup time Data hold time Access time Output disable time Enable pulse Read width Write
Signal RS RS DB7 to DB0 E_RDB
Symbol tAS68 tAH68 tCY68 tDS68 tDH68 tACC68 tOD68 tPW68(R) tPW68(W)
Min. 0 0 300 40 15 10 120 60
(VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Max. Unit Remark 140 100 ns ns ns ns CL = 100 pF
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Serial Interface Characteristics
tCSS CS1B (CS2 = 1) RS tCYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tDSS DB7 (SID) tASS
tCHS tAHS
tWHS tDHS
Figure 32. Serial Interface Characteristics
Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time
Signal DB6 (SCLK) RS DB7 (SID) CS1B
Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS
Min. 250 100 100 150 150 100 100 150 150
Typ. -
(VDD = 2.4 to 3.6V, Ta = -40 to +85C) Max. Unit Remark ns
ns ns ns
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reset Input Timing
tRW RESETB tR Internal status During reset Reset complete
Figure 33. Reset Input Timing
Item Reset low pulse width Reset time
Signal RESETB -
Symbol tRW tR
Min. 1.0 -
(VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Remark Max. Unit 1.0 ns ns
Display Control Output Timing
tDFR CL (OUT) FR
Figure 34. Display Control Output Timing
Item FR delay time
Signal FR
Symbol tDFR
Min. -
(VDD = 2.4 to 3.6V, Ta = -40 to +85C) Typ. Remark Max. Unit 20 80 ns CL = 50 pF
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = "H", C68 = "H")
CS1B CS2 CS1B CS2 RS E_RDB RW_WRB DB0 to DB7 RESETB C68 PS
6800-series MPU
RS E RW DB0 to DB7 RESETB VDD VDD
KS0724
Figure 35. Interfacing with 6800-series (PS = "H", C68 = "H") In Case of Interfacing with 8080-series (PS = "H", C68 = "L")
CS1B CS2 RS RDB WRB DB0 to DB7 RESETB VSS VDD CS1B CS2 RS KS0724 E_RDB RW_WRB DB0 to DB7 RESETB C68 PS
8080-series MPU
Figure 36. Interfacing with 8080-series (PS = "H", C68 = "L") In Case of Serial Interface (PS = "L", C68 = "H or L")
CS1B CS2 RS SID
CS1B CS2 RS DB7(SID) DB6(SCLK) RESETB DB0 to DB5 C68 PS
KS0724
MPU
SCLK RESETB OPEN VDD or VSS VSS
Figure 37. Serial Interface (PS = "L", C68 = "H or L")
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Connections between KS0724 and LCD Panel Single Chip Structure (1/65 Duty Configurations)
(R)
(R)
64 x 132 pixels
(R)
64 x 132 pixels
(R)
SEG0
COMS COM0 : COM31
...........
SEG131
COM32 : COM63 COMS
SEG131
COM32 : COM63 COMS
...........
SEG0
COMS COM0 : COM31
KS0724 (Bottom View)
KS0724 (Top View)
Figure 38. SHL = 1, ADC = 0
Figure 39. SHL = 1, ADC = 1
COM31 : COM0 COMS
KS0724 (Top View)
...........
COMS COM63 : COM32
COMS COM63 : COM32
KS0724 (Bottom View)
............
COM31 : COM0 COMS
SEG0
SEG131
SEG131
SEG0
(R)
(R)
64 x 132 pixels
(R)
64 x 132 pixels
(R)
Figure 40. SHL = 0, ADC = 0
Figure 41. SHL = 0, ADC = 1
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Single Chip Structure (1/55 Duty Configurations)
(R)
(R)
54 x 132 pixels
(R)
54 x 132 pixels
(R)
SEG0
COMS COM0 : COM26
...........
SEG131
COM37 : COM63 COMS
SEG131
COM37 : COM63 COMS
...........
SEG0
COMS COM0 : COM26
KS0724 (Bottom View)
KS0724 (Top View)
Figure 42. SHL = 1, ADC = 0
Figure 43. SHL = 1, ADC = 1
COM26 : COM0 COMS
KS0724 (Top View)
...........
COMS COM63 : COM37
COMS COM63 : COM37
KS0724 (Bottom View)
............
COM26 : COM0 COMS
SEG0
SEG131
SEG131
SEG0
(R)
(R)
54 x 132 pixels
(R)
54 x 132 pixels
(R)
Figure 44. SHL = 0, ADC = 0
Figure 45. SHL = 0, ADC = 1
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KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Single Chip Structure (1/49 Duty Configurations)
(R)
(R)
48 x 132 pixels
(R)
48 x 132 pixels
(R)
SEG0
COMS COM0 : COM23
...........
SEG131
COM40 : COM63 COMS
SEG131
COM40 : COM63 COMS
...........
SEG0
COMS COM0 : COM23
KS0724 (Bottom View)
KS0724 (Top View)
Figure 46. SHL = 1, ADC = 0
Figure 47. SHL = 1, ADC = 1
COM23 : COM0 COMS
KS0724 (Top View)
...........
COMS COM63 : COM40
COMS COM63 : COM40
KS0724 (Bottom View)
............
COM23 : COM0 COMS
SEG0
SEG131
SEG131
SEG0
(R)
(R)
48 x 132 pixels
(R)
48 x 132 pixels
(R)
Figure 48. SHL = 0, ADC = 0
Figure 49. SHL = 0, ADC = 1
59
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
Single Chip Structure (1/33 Duty Configurations)
(R)
(R)
32 x 132 pixels
(R)
32 x 132 pixels
(R)
SEG0
COMS COM0 : COM15
...........
SEG131
COM48 : COM63 COMS
SEG131
COM48 : COM63 COMS
...........
SEG0
COMS COM0 : COM15
KS0724 (Bottom View)
KS0724 (Top View)
Figure 50. SHL = 1, ADC = 0
Figure 51. SHL = 1, ADC = 1
COM15 : COM0 COMS
KS0724 (Top View)
...........
COMS COM63 : COM48
COMS COM63 : COM48
KS0724 (Bottom View)
............
COM15 : COM0 COMS
SEG0
SEG131
SEG131
SEG0
(R)
(R)
32 x 132 pixels
(R)
32 x 132 pixels
(R)
Figure 52. SHL = 0, ADC = 0
Figure 53. SHL = 0, ADC = 1
60
KS0724
PRELIMINARY SPEC. VER. 0.8
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Structure - 65COM (64COM + 1COMS) x 264SEG (132SEG x 2)
(R)
64 x 264 pixels
(R)
SEG131
COM32 : COM63 COMS
...............
SEG0
COMS COM0 : COM31
SEG131
COM32 : COM63 COMS
...............
SEG0
COMS COM0 : COM31
KS0724 (Top View) (Master)
KS0724 (Top View) (Slave)
Figure 54. SHL = 1, ADC = 1 Connect the following pins of two chips each other: - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4
COM31 : COM0 COMS
KS0724 (Top View) (Master)
...................
COMS COM63 : COM32
COM31 : COM0 COMS
SEG0
SEG131
SEG0
KS0724 (Top View) (Slave)
...................
COMS COM63 : COM32
SEG131
(R)
64 x 264 pixels
(R)
Figure 55. SHL = 0, ADC = 0 Connect the following pins of two chips each other: - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4
61
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.8
KS0724
- 130COM (128COM + 2COMS) x 132SEG
COM31 : COM0 COMS
KS0724 ( Top View ) ( Master )
...................
COMS COM63 : COM32
SEG0
SEG131

(R)
128 x 132 pixels
SEG131
COM32 : COM63 COMS
...................
SEG0
COMS COM0 : COM31
KS0724 ( Top View ) ( Slave )
Figure 56. 130COM (128COM + 2COMS) x 132SEG Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 Common / Segment output direction select - Master chip: SHL = 0, ADC = 0 - Slave chip: SHL = 1, ADC = 1
62

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